The present invention relates to a semiconductor integrated circuit device. In particular, it relates to techniques which are effective when applied to a semiconductor integrated circuit device having at least two layers of aluminum wiring, more desirably, a semiconductor integrated circuit device including a DRAM (Dynamic Random Access Memory) having at least two layers of aluminum wiring.
In recent years, DRAMs of 1 [Mbit] or 4 [Mbits] each having two layers of aluminum wiring have been actively developed. They are described in, for example, "Denshi-Zairyo (Electronics Materials)," January 1986, pp. 39-44, and "Nikkei Microdevices, Extra Issue No. 1" issued by Nikkei McGraw-Hill Inc., May 1987, pp. 149-164. In any of these DRAMs, the second layer of aluminum wiring is used as shunt wiring for lowering the resistance of a word line made of a poly-cide. That is, the word line of the poly-cide and the second layer of aluminum wiring are laid in parallel and are connected to each other at predetermined intervals.